With continued scaling of semiconductor devices, various applications are benefiting from and/or requiring the down-scaling of circuits. As part of this effort, 1-transistor 1-capacitor (1T-1C) DRAM circuits have also been scaled down to suit various needs. However, down-scaling has produced problems specific to DRAM cells, such as access transistor leakage and resistance while accessing the stored charge (Qstored) in the capacitor, and difficulties in storing sufficient charge to maintain a good signal to noise ratio while downscaling capacitor dimensions.
Capacitor-less single-transistor (1T) DRAMs have attracted attention, in part due to the lack of the capacitor and the problems associated with the scaling of the capacitor, and to an ability to achieve high device density. While information is stored as different charge levels at a capacitor in conventional 1T/1C DRAM, the 1T DRAM employs floating body effects within the transistor to store the information. The memory effect in 1T DRAM is caused by excess holes in the floating body, which lower the threshold voltage (VTH) of the transistor. During a read operation, a higher drain current is obtained due to the lower threshold voltage for state “1” compared to state “0,” via which the memory state of the device is sensed.
However, implementing 1T-DRAM can be challenging for a variety of applications. For example, retention time can be on the order of 30 μs-10 ms. Upon scaling, this retention time can be reduced as gate length is shortened, and the volume for Qstored is also reduced.
In some implementations, Qstored has been increased using a SiGe quantum well (1T-QW) in the body of a double gate transistor, which can improve the cell performance by increasing the read current. However, such 1T cells with a quantum well can still exhibit a relatively low retention time (e.g., that does not meet International Technology Roadmap for Semiconductors (ITRS) criteria of 64 ms at 85° C.). For instance, during programming, the hole barrier at the source can be insufficient to confine highly energetic holes generated by impact ionization, such that they can easily escape and be collected at the source electrode, hence reducing the sense margin of state ‘1’. As another example, high diode leakage current through the source/drain diode during a hold state tends to remove all the holes stored in the body and hence reduce the retention time. These and other matters have presented challenges to design and implementation of 1-T DRAM memory circuits, for a variety of applications.